The present invention relates to memory integrated circuits (ICs). More particularly, the invention relates to implementation of redundancy in memory ICs.
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials, for example, strontium bismuth tantalum (SBT) can also be used. The ferroelectric material is located between two electrodes to form a ferroelectric capacitor for storage of information. Ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization direction of the ferroelectric capacitor. To change the polarization direction of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 1 shows a pair of bitlines (bitline BL and bitline complement/BL). Each of the bitlines includes a group of memory cells (110a or 110b). The memory cells of a group, each with a transistor 142 coupled to a capacitor 144 in parallel, are coupled in series to form a chain. Such memory architecture is described in, for example, Takashima et al., xe2x80x9cHigh Density Chain ferroelectric random access Memory (chain FRAM)xe2x80x9d, IEEE Jrnl. of Solid State Circuits, vol. 33, pp. 787-792, May 1998, which is herein incorporated by reference for all purposes. A sense amplifier (not shown) is coupled to the bitlines to facilitate access to the memory cell.
The gates of the cell transistors can be gate conductors which are coupled to or serve as wordlines. A selection transistor is provided to selectively couple one end of the chain to its respective bitline. A first block select signal BS0 is used to control selection transistor 130a and a second block select signal BS1 controls selection transistor 130b. A plateline is coupled to the other end of the chain (e.g., PL or/PL). Numerous bitline pairs or columns are interconnected via wordlines to form a memory block.
Redundant memory elements can be provided to repair defective cells. One type of redundancy scheme is referred to as row or wordline redundancy. In row redundancy, the wordline corresponding to the defective cell is replaced with a redundant row of cells via redundancy circuitry. Redundancy schemes allow some defective ICs to be repaired, thus increasing yield which reduces manufacturing costs.
However, in a chained architecture, the wordlines of a block are interdependent. Due to this interdependence, a redundant element or unit has to be the same size as the block. This means that repairing a defective cell in a block requires replacement of the whole block.
Referring to FIG. 2, an array 201 of memory cells arranged in a chained architecture is shown. As shown, the cells of the array are arranged in 32 blocks 240 with one redundant element 220 equal to the size of 1 block. The wordlines are arranged in the vertical direction; the bitlines are arranged in the horizontal direction. Sense amplifier bank 280 is coupled to one side of the array, coupling to the bitlines. The redundant block is located at the edge of the array between the sense amplifier bank and 32 memory blocks. This redundancy scheme would allow for the repair of one or more defects which occur in only one block. However, such redundancy scheme would be ineffective in repairing defects which occur in more than one block. To repair defects which occur in more than one block, additional redundancy elements would be required. The number of fuses needed to implement such a redundancy scheme is 6 (5 for addressing 1 of 32 blocks and 1 for setting redundancy). Thus, conventional redundancy schemes in chained architecture are very inefficient and utilize significant chip area. Additionally, the relatively large number of cells in a redundant element increases the probability of a failure in the redundant element itself.
From the foregoing discussion, it is desirable to provide an improved redundancy in ICs with chained architecture.
The invention relates to improved redundancy schemes to repair defective memory cells. In one embodiment, the integrated circuit comprises a memory matrix having a plurality memory cells interconnected in first and second directions. The plurality of memory cells are separated into a plurality of memory elements. The matrix also includes a redundant memory element having a plurality of redundant memory cells. The redundant memory element is segmented into R sections in the first direction, wherein R is a whole number equal to or greater than 2. One redundant section can be used to repair one or more defects in a memory element section. By separating the redundant element into R sections, one redundant element can be used to repair defects in up to R different memory elements. In one embodiment, one redundant element can be used to repair defects in up to R different memory elements in the different sections.